The rapidly emerging field of MicroElectroMechanical Systems (MEMS) has penetrated a wide array of applications, in areas as diverse as automotives, inertial guidance and navigation, microoptics, chemical and biological sensing, and biomedical engineering. Use of Silicon-On-Insulator (SOI) material is rapidly expanding in both microelectronic and MEMS applications, because of increasing demand for tight limits on wafer specifications, the low cost of SOI, its process flexibility, radiation hardness and compatibility with high-level integration. Significant benefits may be realized by utilizing SOI material to fabricate inertial sensors, chemical and biological sensors, optoelectronic devices, and a wide range of mechanical structures such as microfluidic and microoptical components and systems. In spite of its many advantages, however, use of SOI wafers to build MEMS devices is not widespread, largely because of difficulties in processing the material.
Prior methods for fabricating MEMS devices using a bonded handle wafer include the dissolved wafer process, in which silicon is bonded to glass and the silicon is dissolved away to reveal an etch-stop layer. This etch-stop layer typically comprises a heavily-doped boron-diffused or boron-doped epitaxial layer, but may also consist of a SiGe alloy layer. However, methods that involve the use of a heavily-boron-doped etch stop suffer in several respects, including poor process control, high defect densities, limitations on ultimate thickness of devices, and incompatibility with microelectronic device integration. Insertion of a SiGe alloy layer resolves several of these limitations, but that method suffers from relatively low deposition rates and material property issues. SOI micromachining has demonstrated that a limited number of device types may be successfully constructed, but the build quality is lacking and many design constraints exist.
The principal constraint involves the problems encountered when performing deep reactive-ion-etching (RIE) of the silicon device layer on top of the oxide interlayer; the RIE process tends to attack the underside of the silicon device layer due to charging of the dielectric layer. Steps have been taken by RIE equipment vendors to resolve this problem, and such methods have mitigated these etch effects.
This requirement has led to the development of alternative SOI processes. However, these alternative processes encounter stringent design rules related to pressure differentials across the thin oxide interlayer. Survival of the oxide interlayer is important for the success of alternative SOI processes, but no solution to this problem has previously been proposed.
Thus, there is a need in the art for a method that relieves the constraints for SOI processing.